Memory is a compact circuit that can be embedded on a chip (integrated circuit (IC)). Memory macros often include redundancy to allow for the repair of failing elements. However, memory redundancy takes area and can impact performance, so it necessarily must be limited. For example, efficient use of memory redundancy is necessary in order to maximize memory yield (e.g., it is desired to repair as many failing elements as possible with as few redundant memory elements as possible).
When embedded on a chip with other logic, the ability to test the memory becomes difficult and time consuming. For this reason, it is not uncommon to have a built-in self-test (BIST) mechanism within the chip (i.e., an integrated circuit (IC)) to verify all or a portion of the internal functionality of the IC. The BIST includes Built In Self Repair (BISR) circuitry, which includes a FARR (failing address and repair register). In implementation, the FARR makes the required calculations to fix memory FAILS, e.g., location of a failure, e.g. failed memory element in an array. The FARR, though, takes up valuable space in the memory array.
More specifically, BISR circuitry is often used to determine how to make use of memory redundancy. BISR circuitry is preferred because it allows for on chip self repair (which reduces manufacturing test time and cost because of reduced Automatic Test Equipment (ATE) requirements and interactions) and enables in-system repair operations (where ATE may not be available). Since BISR circuitry is embedded on the chip any mechanism of reducing BISR circuit area while still allowing for efficient/optimum use of memory redundancy is beneficial. Many BISR circuits receive FAIL information and must generate a repair decision within one clock cycle (allowing the BISR circuitry to handle a new FAIL on the next cycle, back to back FAILS being a possible occurrence).
In an effort to test “at speed” and “at frequency”, the BIST (i.e., FARR) has to operate at the same frequency of the memory array. However, for the FARR to achieve such frequency, optimization results in duplication of logic (parallelism). This results in valuable area requirements for the FARR. In operation, though, the memory array is working at a frequency that may be higher than the remaining logic used for testing the memory array (e.g., BIST, BISR, FARR).
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.